Integrated circuits, or ICs, are created by patterning a substrate and materials deposited on the substrate. The substrate is typically a semiconductor wafer. The patterned features make up devices and interconnections. This process generally starts with a designer creating an integrated circuit by hierarchically defining functional components of the circuit using a hardware description language. From this high-level functional description, a physical circuit implementation dataset is created, which is usually in the form of a netlist. This netlist identifies logic cell instances from a cell library, and describes cell-to-cell connectivity.
Many phases of these electronic design activities may be performed with computer aided design (CAD) tools or electronic design automation (EDA) systems. For example, an integrated circuit designer may use a set of layout EDA application programs, such as a layout editor, to create a physical integrated circuit design layout from a logical circuit design. The layout EDA application uses geometric shapes of different materials to create the various electrical components on an integrated circuit and to represent electronic and circuit IC components as geometric objects with varying shapes and sizes. After an integrated circuit designer has created an initial integrated circuit layout, the integrated circuit designer then verifies and optimizes the integrated circuit layout using a set of EDA testing and analysis tools. Verification may include, for example, design rule checking to verify compliance with rules established for various IC parameters. The EDA layout editing tools are often performed interactively so that the designer can review and provide careful control over the details of the electronic design.
Typically, geometric information about the placement of the nodes and components onto the chip is determined by a placement process and a routing process. The placement process is a process for placing electronic components or circuit blocks on the chip and the routing process is the process for creating interconnections between the blocks and components according to the specified netlist. The task of all routers is the same—routers are given some pre-existing polygons consisting of pins on cells and optionally some pre-routes from the placers to create geometries so that all pins assigned to different nets are connected by wires and vias, that all wires and vias assigned to different nets do not overlap, and that all design rules are obeyed. That is, a router fails when two pins on the same net that should be connected are open, when two pins on two different nets that should remain open are shorted, or when some design rules are violated during routing.
A layout file is created from the placement and routing process, which assigns logic cells to physical locations in the device layout and routes their interconnections. The physical layout is typically described as many patterned layers, and the pattern of each layer is described by the union of a set of polygons. The layout data set is stored, for example in GDSII (“Graphic Data System II”) or OASIS (“Open Artwork System Interchange Standard”) formats. Component devices and interconnections of the integrated circuit are constructed layer by layer. A layer is deposited on the wafer and then it is patterned using a photolithography process and an etch process.
One or more photomasks are created from the layout file for the photolithography of each layer. Photomasks are used to transfer the layout pattern onto the physical layer on the wafer. A photomask, or mask, provides an image of the desired physical geometries of the respective integrated circuit layer. Passing light through the mask projects the layout pattern for the layer onto the wafer. An imaging lens system projects and focuses the layout onto the substrate. The projected light pattern interacts with a photosensitive resist coating on the wafer and, resist portions that are exposed to light are rendered either soluble or insoluble in a developer solution, depending on the type of the photoresist. Accordingly, the mask pattern is transferred into the photo-resist by optical projection and chemical reactions. The photo-resist pattern is subsequently transferred to an underlying layer by an etch process. Most commonly, plasma containing chemically-selective reactive ions is used to etch high-aspect ratio trenches and holes with close to vertical sidewalls.
With a continuing desire to provide greater functionality in smaller packages and the evolution of system-on-chip and mixed-signal designs, IC feature geometries are being driven to smaller and smaller dimensions. However, the ability to project an accurate image of increasingly smaller features onto the wafer is limited by the wavelength of the light used, and the ability of the lens system. For deep sub-micron semiconductor manufacturing process, such as processes at feature sizes of 22 nm and below, the layout geometries on a single layer normally cannot be printed on silicon with a single lithography mask except with great difficulty and/or manufacturing defects/problems. To address this problem, the combination of two masks can be used to create the geometries for a single layer. This approach is often referred to as “double pattern” or “double patterning” technology.
While this new technology theoretically may be used to manufacture semiconductor devices, EDA tools do not yet exist which can efficiently implement routing for double patterning designs that are correct-by-construction. Instead current approaches require post-route layout decomposition and re-routing to fix conflicts. The problem with this type of approach is that it can result in a large number of errors during layout decomposition, which could be impossible to fix, or if even fixable, would require an excessive amount of time and/or resource cost to find a solution.
Therefore, there is a need for an improved approach to implement efficient routing for double-patterning lithography.